1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a multilayered wiring structure.
2. Description of the Related Art
A semiconductor device manufactured by conventional techniques will be described with reference to FIG. 1. FIG. 1 is a sectional view showing the semiconductor device manufactured by conventional techniques.
The semiconductor device having a multilayered wiring structure formed by conventional techniques comprises an insulating layer 26 formed on a semiconductor substrate 21, a lower wiring layer 22 formed on the insulating layer 26, an insulating layer 23 formed on the lower wiring layer 22 and having a contact hole 25 in a predetermined contact region, and an upper wiring layer 24 formed on the insulating layer 23 and connected to the lower wiring layer 22 through the contact hole 25. In this semiconductor device, after the upper wiring layer 24 is formed, annealing is performed, for example, to form a protective layer on the upper wiring layer 24.
When annealing is performed according to the conventional technique, the lower wiring layer 22 connected to the upper wiring layer 24 through the contact hole 25 thermally expands to push out the upper wiring layer 24 through the contact hole 25 and to thus cause an abnormal geometry such as a projection on the upper wiring layer 24. When the projection or the like extends laterally, lines of the upper wiring layer 24 are connected to each other to result in short-circuiting. Even if the of the lines wiring layer 24 are not connected to each other, a distance between the lines is decreased to form a void in the insulating layer or the like on the wiring layer. When thermal stress acts on the insulating layer having a void, the projection grows to cause interwiring short-circuiting, thus degrading reliability. When the projection or the like extends vertically, flatness of the upper wiring layer 24 is degraded when a wiring layer is to be further formed on the upper wiring layer 24. In addition, the influences of thermal expansion become conspicuous when the area of the lower wiring layer 22 is larger than that of the upper wiring layer 24.